PCI (patent pending)

The PCI controller is powerful and flexible supporting several levels of interface sophistication. At the lowest level it can serve as a PCI bus target with modest transfer requirements for high performance applications. The PCI interface controller can become a bus master to attain the PCI local bus peak transfer capability.

Our PCI confirms to Special Interest Group local bus 2.2 specification compliance. It supports PCI initiator / target operation. It is a 32 / 64 bit and operates upto 66 Mhz. The core is available as technology and library independent.

[Click for data sheets]

MPEG-2 Video Decoder (IP CORE)

Description

MP2VD is a solution for MPEG Video Decoder application to support both ISO/IEC 13818-2 (MPEG2) and ISO/IEC 11172-2 (MPEG1) video stream decoding. It includes various high performance hardware computing blocks for video processing. This core can be used in various applications.

  • Set Top Box
  • Digital TV
  • MPEG-2 Camera
  • PC Graphics
  • HDTV
  • DVD

Features

Standard Compliance
ISO/IEC 13818-2 (MPEG-2) Video Decoding

  • High quality, real time decoding (I, B, P)
  • Supports MP@ML, MP@HL
  • Decodes PAL (720x576 @ 25 frames/sec) & NTSC (720x480 @ 29.97 frames/sec)
  • Decoding rate: variable up to 60Mbps
  • Video output
  • 8 bit YCbC r format at 4:2:2 or 4:2:0 format
  • YCbCr to RGB conversion picture formatting
  • Supports ISO/IEC1/172-2 MPEG-1 Video Decoding
  • Error concealment I frame motion vectors
  • Supports for user data insertion in decoded stream
  • On-chip memory interface controller
  • Supports user defined quantization matrix tables

[Click for data sheets]

MPEG 4 VIDEO CODEC IP

Features

Hardware Implementation of ISO/IEC/14496-2 standard targeted for low bit rate applications.

Compact design with low area and low power

Implemented in VHDL and technology independent for mapping to ASIC/FPGA implementation.

Uses custom proprietary algorithms for the implementation of core blocks, developed with emphasis on performance.

FPGA Demonstration Board available

  • Target Applications
  • Video- Phones
  • Video-on-demand
  • Video-conferencing
  • Tele-medicine
  • Video-surveillance
  • Video-mail

Specifications

ENCODER

  • PROFILE Simple profile
  • LEVEL Level 3
  • Video in Y,Cb,Cr (4:2:0)
  • Maximum bit rate 384Kbps
  • Frame size CIF/QCIF
  • Frame rate 30 fps
  • Motion estimation
  • Half pel motion estimation
  • Search range ±32
  • Max number of objects 4
  • Feature Extraction with coupling with ME

DECODER

  • High quality, real-time decoding (I, P)
  • Supports Simple profile level3
  • Image size: CIF,QCIF
  • Bit rate: up to 384 Kbps
  • Video output - 8 bit Y, Cb, Cr
  • Frame rate - 30Fps
  • Half pel motion compensation
  • Unrestricted motion compensation
  • Block based architecture
  • Generic Implementation for any size

[Click for data sheets]

PCI Rev2.2 Compliance Core

The PCI Rev2.2 Compliance Core was an Intellectual Property of U & I. It provides a complete solution for interfacing to the PCI bus. The PCI core is RTL synthesizable which is available in 64 / 32bit 66 MHz PCI Initiator / Target core. It is capable of addressing all configurations of the PCI bus. This core allows easy connection to a wide variety of memories, I/O peripherals, Network Controllers and Various Processors. The core handles all PCI protocol and timing requirements. The PCI core offer synchronous or asynchronous application interfaces. It can be used for high speed Applications up to 528 MBPS. The main features of PCI core includes,

  • PCI Special Interest Group local bus 2.2-specification compliance.
  • Supports PCI Initiator/Target operation.
  • 32 & 64-bit application data path support.
  • Operation up to 66Mhz.
  • Unlimited burst supported in Master & Target Mode.
  • Configurable on-chip FIFOs (optional) for maximum burst speed.
  • Memory read/write.
  • I/O Read/Write.
  • Configuration read/write.
  • Dual Address cycles support (Both for Master & Target).
  • Fast back-to-back transactions.
  • Master Abort and Disconnect facilities.
  • Target-Retry and Termination, upon request from the Backend Device.
  • INTx# signals are provided.

Core Specs

  • Technology: Independent
  • Speed: 33/66 MHz
  • Compliance: PCI Special Interest Group local bus 2.2 specification compliant

The developed PCI Core was targeted for 0.5mm (Hyundai) & 0.18mm (TSMC) in Synopsys Design Compiler, both functional and timing Simulation was done in Cadence Affirma environment (LDV3.2). PCI functional and timing simulations were checked with PCI 2.2 Checklists for Rev2.2 compliance.

( The PCI Core designed and developed by U & I Design Team is now being “AFCP Controller” for UNIWIDE Technologies, “Trishuul”- a Hardware solution for E-Security. Also in “NetMon” - a Hardware solution for Network monitoring.)

[Click for data sheets]

 

[Back to Top]

IP's| Trishuul | Sypderwatch | Wap Stack | Satel | Satmove |